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Ordering number : ENA1003
LV24030LP
Overview
Bi-CMOS IC
FM Tuner IC for Small Portable Equipment
The LV24030LP is FM tuner IC's that requires absolutely no external components for tuning. They incorporates not only the FM tuner functions as well in a compact VQLP package with dimensions of only 4.0x4.0x0.8mm. These IC's are simply ideal for incorporating FM tuner functions into mobile phones and other small mobile set where space is always at a premium.
Functions
* FM FE * FM IF * MPX stereo decoder * Tuning * Standby
Features
* No external components * No alignments necessary * Fully integrated low IF (140kHz) selectivity and demodulation * Built in adjacent channel interface total reduction (no 114kHz, no 190kHz) * Due to new tuning concept, the tuning is independent of the channel spacing * Very high sensitivity due to integrated low noise RF input amplifier * Very low power standby mode. No power switch circuitry required * MPX output for RDS application * 3-wire bus interface (Date, Clock, NR-W) * Digital AFC-Tuner locks to frequency after tuning sequence * 4 level programmable Soft Mute * 4 level Programmable Stereo Blend
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
13008 TI IM 20080124-S00004 No.A1003-1/14
LV24030LP
Continued from preceding page.
* In combination with the host, fast, low power operation of present mode, manual search, automatic search and automatic present store are possible * Covers all Japanese, European and US bands * Built in voltage stabilizer * Stereo pilot signal Canceller
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Symbol VCC max VDD max Digital input voltage VIN1 max VIN2 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Conditions Analog block supply voltage Digital block supply voltage Clock, Data, NR_W External_clk_in Ta70C, Mounted on a specified board * Ratings 5.0 4.5 VDD+0.3 VDD+0.3 140 -20 to +70 -40 to +125 Unit V V V V mW C C
Note: Mounted on a specified board: 40mmx50mmx0.8mm, glass epoxy Operating Condition at Ta = 25C
Parameter Recommended supply voltage Symbol VCC VDD Operating supply voltage range VCC op VDD op VIO op Interface voltage Conditions Analog block supply voltage Digital block supply voltage Ratings 3.0 3.0 2.6 to 4.0 2.5 to 4.0 1.8 to 4.0 Unit V V V V V
Note: The VIO application voltage must be either equivalent to VDD or the VDD value or less. (VIO VDD) Interface Block Allowable Operation Range at Ta = -20 to +70C, VSS = 0V
Parameter Supply voltage Digital block input (including the external clock) Digital block output Symbol VDD VIH VIL IOL VOL Clock input operating frequency External clock operating frequency fclk fclk_ext High level input voltage range Low level input voltage range Output current at Low level Output voltage at Low level IOL=2mA (Pin5) clock frequency for 3wire_bus (Pin12) clock frequency for external input 32k Conditions min 2.5 0.7VIO 0 2.0 0.6 0.7 20M Ratings typ max 4.0 VIO 0.6 V V V mA V MHz Hz Unit
Note: External clock input (pin12) allows also input of the sine wave signal.
No.A1003-2/14
LV24030LP
Operating Characteristics at Ta=25C, VCC=3.0V, VDD=3.0V, Soft Mute/Soft Stereo=off, with the specified test circuit. Output level setting is for the maximum output setting by setting Bit 4 and Bit 5 (Audio output level bits) of Address 04h of the control register map to "1" respectively. In other cases, the IF_BW set Bit value is when the value has been set to 65% of the IF_OSC set Bit value. (Register setting for IF_OSC set =140kHz and IF_BW=140kHz*0.65)
Parameter Current drain (in operation) Symbol ICCA ICCD Current drain (in standby) ICCA ICCD FM receive band FM receiving characteristics MONO : fc=80MHz, fm=1kHz, 22.5kHz dev. Note that Soft_stereo, Soft_and mute functions are OFF. 3dB sensitivity Practical sensitivity 1 Practical sensitivity 2 (Reference) Demodulator output Channel balance Signal-to-noise ratio Total harmonic distortion 1 (MONO) Total harmonic distortion 2 (MONO) Field intensity display level Mute attenuation -3dB LS QS1 QS2 VO CB S/N THD1 THD2 FS Mute-Att 60dBV, 22.5kHz dev. output standard, -3dB input. Input level with S/N=30dB De-emphasis=75s SG open display Input level with S/N=26dB De-emphasis=75s, SG terminal display 60dBV, pin 18, pin 19 output 60dBV, pin 18 / pin 19 output 60dBV, pin 18, pin 19 output 60dBV, pin 18, pin 19 output, 22.5kH dev. 60dBV, pin 18, pin 19 output, 75kH dev. Input level at which FS1 changes to FS2, Reg04_bit3=0 60dBV, pin 18, pin 19 output 3 60 80 -2 48 5 8 1.1 110 0 58 0.4 1.3 10 70 1.5 3.0 20 160 2 17 16 dBV EMF dBV V mV dB dB % % dB dB F_range Conditions min Measurement at pin 13 with 60dB input in the analog block, Monaural input Measurement at pins 3 and 4 with 60dB input in the digital block Measurement at pin 13 in the standby mode of the analog block Measurement at pins 3 and 4 in the standby mode of the digital block. When mounted to PCB with SANYO recommended conditions 76 Ratings typ 12 0.3 3 3 max 17 mA 0.8 30 A 30 108 MHz Unit
FM receive characteristic STEREO characteristics : fc=80MHz, fm=1kHz, VIN=60dBV, Pilot=10%(7.5kHz dev.) Separation Total harmonic distortion (Main) SEP THD-ST L-mod, Pin19, pin18 output L+R signals =30%(22.5kHz dev.) Main-mod (for L+R input), Pin19, pin18 output IHF_BPF, L+R=30%(22.5kHz dev.) 20 35 0.6 1.8 dB %
No.A1003-3/14
LV24030LP
Package Dimensions
unit : mm (typ) 3347
TOP VIEW 4.0 SIDE VIEW (0.0625) BOTTOM VIEW 0.35
(0.15)
4.0
0.5
2 0.25 0.5
1 (0.75)
0.0NOM
0.85MAX
SIDE VIEW
SANYO : VQLP24(4.0X4.0)
Block Diagram and Pin Assigment
Line_out_R
Vstabi
24
(0.75)
0.35
MPX
Line_out_L Buffer AMP FM Demodulator FM Selectivity Filter
AFC Tuning
Voltage Stabilizer Source Mixer Stereo Decoder
VCC
AFC
Ext_CLK_IN
To Each Block
De-emphasis
Tuning System Power Management Digital Interface
RF and FM Quadrature Mixer GND
Quadrature Oscillator
To Each Block
To Each Block
NRW
FM_ANT1
FM_ANT2
VDD
VIO
CLK
DATA
Top view
No.A1003-4/14
LV24030LP
Pin Discription
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FM-ANT1 FM-ANT2 VI/O VDD CLOCK DATA NR_W Package-GND Package-GND Package-GND Package-GND Ext_CLK_IN VCC NC Vstabi. AFC MPX LINE-OUT-R LINE-OUT-L Package-GND Package-GND Package-GND Package-GND GND Stabilizer voltage AFC control bias MPX-signal output Radio Rch Line-output Radio Lch Line-output GND for package-shield GND for package-shield GND for package-shield GND for package-shield GND (Analog and Digital GND) Name Description Antenna input Antenna GND Digital interface supply voltage Digital supply voltage Digital interface Clock Digital interface DATA Digital interface Read/Write GND for package-shield GND for package-shield GND for package-shield GND for package-shield Reference clock-source input for measurement Analog supply voltage Remarks FM signal input point Connect to GND with capacitor Connect to power supply Connect to power supply Control pin Control pin Control pin Connect to GND Connect to GND Connect to GND Connect to GND Control pin Connect to GND if not used Connect to power supply Open Open Put capacitor between 16 pin and GND Otherwise, open if not used Open Output pin Output pin Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND 2.3V 1V 1V 2.5V 1.1 DC_bias 1V 1V
Line_out_R
Vstabi
Line_out_L Package-GND Package-GND
13
VCC
MPX
AFC
NC
Ext_CLK_IN Package-GND Package-GND
LV24030LP
Package-GND Package-GND GND 1 FM_ANT1 FM_ANT2 DATA VDD CLK VIO Package-GND Package-GND NRW
Top view
No.A1003-5/14
LV24030LP
The PCB mounting conditions which cover FM receiving frequency range 76MHz to 108MHz LV24030LP has an inductor for local oscillator on the package bottom side. In order to cover the receiving frequency range of 76MHz to 108MHz, provide the GND layer to the first layer of Side A of PCB that is directly under the package bottom side, as shown in the figure. Printed circuit board
LV24030LP
X=0mm LAYER
PCB layout recommendations
4.0x4.0 4.0x4.0
0.25
0.75
PCB GND Layer
0.50
1.92 3.08
0.35 0.50 X=3.00
0.50
IC substrate LV24030LP
Recommended GND layer for PCB substrate directly under IC
With this SPL, the receiving frequency is measured under the following conditions: The X-value can be set freely between Min=2.4mm and Max=3.0mm with reference to IC. (The X-value for SANYO Demo Board is 2.8mm.) The Y-value can be set freely between Min=2.0mm and Max=3.0mm with reference to IC. (The Y-value for SANYO Demo Board is 2.6mm.) Avoid providing another wiring within 0.4mm of bottom layer of PCB_GND as much as possible.
No.A1003-6/14
0.70
Y=2.60
0.34
2.60
0.70
LV24030LP
Serial Data Timing
* Write timing
tW NR_W tDL DATA tCL VIH VIL tCH tHD
CLOCK
Symbol tW tDL tHD tCH tCL Delay from command to data
Conditions min 750 750 750 750 750
Ratings typ max
Unit ns ns ns ns ns
Delay from data stable to data latch time Data Hold time Clock High-level time Clock Low-level time
* Read timing
tW NR_W tSU DATA tHD
CLOCK
Symbol tW tSU THD
Conditions min Delay from command to 1st data bit Data Setup time Data hold time 350
Ratings typ max
Unit ns 350 350 ns ns
* External clock timing (Pin 31)
tCH CLK_IN VIH VIL
tCL
Symbol tCH tCL Clock High-level time Clock Low-level time
Conditions min 35 35
Ratings typ max
Unit ns ns
No.A1003-7/14
LV24030LP
Digital Interface Specification (reference)
* 3-wire bus (For communication line) Access to the LV24030 is done through the 3-wire bus.
CLOCK NR_W DATA Clock Write/read control Data is written into LC24030 when the bidirectional communication line NR_W is H and is read from LV24030 when NR_W is L.
LV24030 has a function to notify occurrence of interruption by means of change in the DATA line. If interruption is to be made, it is essential that the controller supports interruption by change of the DATA line. When the timing necessary for frequency measurement cannot be generated from the controller, it is necessary to input the external clock (oscillator or 32kHz crystal) to the CLK_IN pin of LV24030. * Register map
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h Register name CHIP_ID NA CNT_L FM_OSC AUDIO_CTRL MSRC_SEL CTRL_STAT RADIO_STAT STEREO_CTRL FM_CAP PW_SCTRL SD_OSC CNT_CTRL CNT_STAT IF_OSC IF_BW RADIO_CTRL1 CNT_H Access R R W W W R R W W W W W R W W W R Counter value low byte DAC control for FM-RF oscillator Audio Control Measure source select Control status Radio station status Stereo Control RM-RF CAP bank DAC setting Power and soft control DAC control for stereo decoder oscillator Counter control Control status DAC control for IF oscillator IF Bandwidth Radio control 1 Counter value high byte Chip identification Operation
Registers with blank colum are not defined and should not be accessed.
No.A1003-8/14
LV24030LP
Register Description (For each resister content)
Register 00h-CHIP_ID-Chip Identify Register (Read only)
7 6 5 4 ID[7:0] Bit 7-0: ID[7:0]: 8-bit chip ID LV24030:02h 3 2 1 0
Register 02h-CNT_L-Counter Value Low Register (Read-only)
7 6 5 4 CNT_LSB[7:0] Bit 7-0: CNT_LSB[7:0]: Lower 8-bit value of the 16 bit counter 3 2 1 0
Register 03h-FM_OSC-FM RF Oscillator Register (Write-only)
7 6 5 4 FMOSC[7:0] Bit 7-0: FMOSC[7:0]: DAC value to control the FM RF oscillator (fine step) 3 2 1 0
Register 04h - AUDIO_CTRL - Audio Control Register (Write-only)
7 Reserved Bit 7-6: Bit 5-4: Reserved: Fixed at 0 nVOL[1:0]: Audio output level 11b = Maximum output level 10b = Output level 3 01b = Output level 2 00b = Minimum output level Bit 3: SF5dB 0 = No FS increase by 5dB 1 = FS+5dB Bit 2: DEEMP: De-emphasis bit 0 = De-emphasis 50s 1 = De-emphasis 70s Bit 1: AMUTE_L: Audio mute bit 0 = Mute 1 = Mute cancelled Bit 0: SE_FM: FM radio select 0 = FM radio disabled 1 = FM radio enabled 6 5 nVOL1 4 nVOL0 3 Reserved 2 DEEMP 1 AMUTE_L 0 SE_FM
No.A1003-9/14
LV24030LP
Register 05h-MSRC_SEL-Measurement Source Select Register (Write-only)
7 MSR_O Bit 7 6 AFC_LVL 0 = No output 1 = Output (for testing) Bit 6 AFC_LVL: AFC trigger level 0 = AFC is always active 1 = AFC is only active when field strength is above 20dBV Bit 5 DIR_AFC: AFC operation direction 0 = AFC reverse operation (for testing) 1 = AFC normal operation Bit 4 RST_AFC: AFC reset 0 = Normal operation 1 = Resets AFC to the center of control range Bit 3 MSS_AFCS: Detects the AFC status by the data line 0 = AFC status read disabled 1 = AFC status read enabled With this bit set to "1" and with MSR_O = 1, the state outside the AFC control range can be detected from the change of the DATA line. In case of the state outside the AFC control range, the DATA line changes from L to H. Bit 2 MSS_SD: Stereo decoder oscillator measurement 0 = Disable stereo decoder oscillator measurement 1 = Enable stereo decoder oscillator measurement Bit 1 MSS_RF16: RF/16 measurement 0 = RF/16 oscillator measurement disabled 1 = RF/16 oscillator measurement enabled Bit 0 MSS_IF: IF oscillator measurement 0 = Disable IF oscillator measurement 1 = Enable IF oscillator measurement Note: Be sure that only one of MSS_XX bits is enabled. The FM RF frequency is divided to 1/16 and input into the measuring circuit. 5 DIR_AFC 4 RST_AFC 3 MSS_AFCS 2 MSS_SD 1 MSS_RF16 0 MSS_IF
MSR_O: Outputs VCO of IF,SD, and RF frequencies to the data pin (for testing)
Register 06h-CTRL_STAT-Control Status Register (Read-only)
7 REV3 Bit 7-4 Bit 3 6 REV2 REV[3:0]: 0Fh AFC_UP: AFC adjustment up-direction 0 = Center value 1 = RF frequency adjusted in the up-direction Bit 2 AFC_DN: AFC adjustment down-direction 0 = Center value 1 = RF frequency adjusted in the down-direction Bit 1 COV_FLG: Counter overflow flag 0 = No overflow 1= Counter overflow Bit 0 AFC_FLG: AFC out of range bit 0 =AFC is within control range 1 =AFC is out of control range Note: COV_FLG is cleared when CLR_CNT1 bit of CNT_CTRL register is set to "1." 5 REV1 4 REV0 3 AFC_UP 2 AFC_DN 1 COV_FLG 0 AFC_FLG
No.A1003-10/14
LV24030LP
Register 07h - RADIO_STAT - Radio Station Status Register (Read-only)
7 RSS_MS Bit 7 RSS_MS: mono/stereo determination 0 = mono 1 = stereo Bit 6-0 RSS_FS[6:0]: Field Strength bit 1111111b = Field Strength<10dBV 0111111b = Field Strength 10 to 20dBV 0011111b = Field Strength 20 to 30dBV 0001111b = Field Strength 30 to 40dBV 0000111b = Field Strength 40 to 50dBV 0000011b = Field Strength 50 to 60dBV 0000001b = Field Strength>70dBV Note: +5dB for Register 04h bit3 = 1 6 5 4 3 RSS_FS 2 1 0
Register 08h-STEREO_CTRL-Stereo Control Register (Write-only)
7 PICMPS Bit 7 6 SD_PM 0 = Disable 1 = Enable Bit 6 SD_PM: Stereo Decorder PLL Mute 0 = PLL ON (for normal operation) 1 = PLL OFF (for measurement, etc.) Bit 5 ST_M: mono/stereo changeover 0 = Stereo 1 = mono Bit 4 FRCST: Forced stereo 0 = Normal 1 = Forced stereo (for testing) Bit 3 IF_PM_L:IF PLL Mute 0 = PLL OFF (for measurement) 1 = PLL ON (for normal operation) Bit 2 DCFB_SPD: DC feedback speed 0 = Normal speed (for normal operation) 1 = High speed (for testing) Bit 1 Bit 0 DCFB_OFF: DC Feedback control Fixed at 0 AGCSP: AGC speed control 0 = Normal speed 1 = High speed Note: With this bit ON, rise of the Field strength becomes faster. 5 ST_M 4 FRCST 3 IF_PM_L 2 DCFB_SPD 1 DCFB_OFF 0 AGCSP
PICMPS: Pilot compensation
Register 09h-FM_CAP-FM RF Capacitor Bank Register (Write-only)
7 Bit 7-0 6 5 4 FMCAP[7:0] FMCAP[7:0]: FM RF frequency CAP bank (rough adjustment) 3 2 1 0
No.A1003-11/14
LV24030LP
Register 0Ah-PW_SCTRL-Power and Soft Control Register (Write-only)
7 6 SS_CTRL Bit 7-5 SS_CTRL: Soft stereo control 000b = Soft stereo level 3 001b = Soft stereo off 010b = Soft stereo level 1 100b = Soft stereo level 2 Bit 4-2 SM_CTRL: Soft mute control 000b = Soft mute level 3 001b = Soft mute off 010b = Soft mute level 1 100b = Soft mute level 2 Bit 1 EXTCLK: External clock type 0 = Crystal 1 = Oscillator Bit 0 PW_RAD: Radio power 0 = Radio OFF 1 = Radio ON 5 4 3 SM_CTRL 2 1 EXTCLK 0 PW_RAD
Register 0Bh-SD_OSC-Stereo Decoder Oscillator Register (Write-only)
7 6 5 4 SDOSC[7:0] Bit 7-0 SDOSC[7:0]: Stereo Decoder oscillator DAC 3 2 1 0
Register 0Ch-CNT_CTRL-Counters Control Register (Write-only)
7 CNT1_CLR Bit 7 6 CTAB2 0 = Normal mode 1 = Clears the counter1 Bit 6-4 CTAB[2:0]: Sets the counter2 TAB value 000b 001b 010b 011b 100b 101b 110b 111b Bit 3 Stop after 2 counts Stop after 8 counts Stop after 32 counts Stop after 128 counts Stop after 512 counts Stop after 2048 counts Stop after 8192 counts Stop after 32768 counts 5 CTAB1 4 CTAB0 3 SWP_CNT_L 2 CNT_EN 1 CNT_SEL 0 CNT_SET
CNT1_CLR: Clears the counter1
SWP_CNT: Counter swap control (0 for swap) 0 = Clock source 1 to counter 2, clock source 2 to counter 1 (swapping) 1 = Clock source 1 to counter 1, clock source 2 to counter 2 (no swap)
Bit 2
CNT_EN: Count start 0 = Count stop 1 = Count start
Bit 1
CNT_SEL: Counter select 0 = Counter1 used for measurement 1 = Counter2 used for measurement
Bit 0
CNT_SET: Set counters bit 0 = Normal mode 1 = Set both counter 1 and counter 2 to FFFFh and keep them set
Register 0Dh-CNT_STAT-Counters Status Register (Read-only)
7 Reserved Bit 7 Bit 6 6 CNT_RDY Reserved: 1 CNT_RDY: Count over flag 0 = Counting 1 = Count over Note: CNT_RDY is cleared by setting the CLR_CNT 1 bit of CNT_CTRL register to"1." Bit 5-0 Reserved: 0 5 4 3 Reserved 2 1 0
No.A1003-12/14
LV24030LP
Register 0Eh-IF_OSC-IF Oscillator Register (Write-only)
7 6 5 4 IFOSC[7:0] Bit 7-0 IFOSC[7:0]: IF oscillator DAC 3 2 1 0
Register 0Fh-IF_BW-IF Bandwidth Register (Write-only)
7 6 5 4 IFBW[7:0] Bit 7-0 IFBW[7:0]: IF band width 3 2 1 0
Register 10h-RADIO_CTRL1-Radio Control 1 Register (Write-only)
7 VREF2 Bit 7 6 VREF 5 STABI_BP 4 EN_MEAS 3 EN_AFC 2 AGC_SLVL[1:0] 1 0 AFC_SPD
VREF2: VREF2 control bit 0 = VREF2 is ON 1 = VREF2 is OFF
Bit 6
VREF: VREF control bit 0 = VREF is ON 1 = VREF is OFF
Bit 5
STABI_BP: Voltage stabilizer (regulator) control 0 = Internal voltage is Vstabi (normal operation) 1 = Internal voltage is VCC (stabi bypassed) EN_MEAS: Measurement mode 0 = Normal mode 1 = Measurement mode
Bit 4
Bit 3
EN_AFC: AFC control 0 = AFC OFF 1 = AFC ON
Bit 2-1 Bit 0
AGC_SLVL[1:0]: AGC set level Default = 0 AFC_SPD: AFC speed control 0 = AFC speed 3Hz 1 = AFC speed 8kHz (for testing)
Register 11h-CNT_H-Counter Value High Register (Read-only)
7 6 5 4 CNT_MSB[7:0] Bit 7-0 CNT_MSB[7:0]: Upper 8-bit value of the 16 bit counter 22F 0.1F 0.1F VCC 3 2 1 0
Test Circuit
Line_out_R
External_CLK_IN 13 Line_out_L 0.1F
VCC Voltage source
SW
Package GND GND FM_SG 1000pF 75 1 VIO CLOCK CLOCK 200 DATA VDD
Package GND NR_W
DATA 200
0.1F VDD Voltage source SW
MPU
External_ CLK_IN
1000pF
NR_W 200 200
No.A1003-13/14
LV24030LP
Application Circuit
Line_out_R Not necessary when the DC cut capacity 1.0F is on the receive side VCC 22F 0.1F Changeover of resistor possible depending on the state of power supply
4.7H or R:4.7 External_CLK_IN VCC Voltage source SW
13 Line_out_L 0.1F
Package GND GND FM_ANT 100 to 1000pF 27pF 47pF CLOCK 120nH Winding type 0.1F DATA 1
Package GND NR_W 200 to 1k
VIO
CLOCK
DATA
VDD
R1
R2
R3 NR_W
R4 External_ CLK_IN
4.7H
MPU
2.2H or R:12 VDD Voltage source SW Changeover of resistor possible depending on the state of power supply
Note1: Vale of Extenal Component is just reference. Please set most sutable value under Acutual_ operation. Note2: Please take Consideration of most suitable_value, as for antenna application Note3: We recomend to put R1,R2,R3,R4 for interface between MPU and IC. Note4: Please put Capacitor Between VDD and GND also, put Capacitor Between VCC and GND as shown on application. Note5: As for AFC pin (16 pin), usually it is recommended not to connect anything. AFC can be operated more smoothly by putting capacitor between 16 pin and GND.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of January, 2008. Specifications and information herein are subject to change without notice.
PS No.A1003-14/14

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